Active pull up apparatus for a data bus

ABSTRACT

An active pull up configuration for data bus lines unaffected by integral pull up resistors within subsystems. The present application generally relates to digital systems comprising a plurality of power supply levels and data buses. More particularly, this invention relates to digital system comprising subsystems connected by common buses that require automatic charging of certain buses or lines. In a television signal processing apparatus using an I2C bus and using the present invention according to a exemplary embodiment of the present invention, a first device operative in a first mode of operation and a second device operative in said first mode of operation and a second mode of operation wherein said first circuit and said second circuit are both connected by the I2C bus wherein said each data bus line requiring an active pull up is connected to a first power supply via a first resistor integrated within the first device and connected to a second power supply via a second resistor integrated within said second device. The first resistor is electrically isolated from the first power supply during the second mode of operation and electrically connected to the first power supply during the second mode of operation.

This application claims the benefit, under 35 U.S.C. § 365 ofInternational Application PCT/US04/29522 filed Sep. 9, 2004, which waspublished in accordance with PCT Article 21(2) on Mar. 17, 2005 inEnglish and which claims the benefit of U.S. provisional patentapplication No. 60/501,894 filed Sep. 9, 2003.

FIELD OF THE INVENTION Background of the Invention

The present application generally relates to digital systems comprisinga plurality of power supply levels, operating modes and at least onedata bus. Systems such as television systems, home and portable audiosystems, and satellite reception systems may contain more than one powersupply level or operating mode. Examples of operating modes would be runmodes, where the system is operating in its primary intended mode ofoperation, such as with a television system, where the system isreceiving a television signal, decoding the signal and displaying theimage on a television screen. In a standby mode, a system is in asecondary operating mode, typically performing only a subset of thefunctions performed in the run mode, and possibly a number of functionsnot normally performed in run mode operation. In a television system, nopicture is displayed and no audio is played, but some portions of theelectronics may be powered to receive broadcast administrative or guidedata, or waiting for remote control commands to resume run mode. Duringthe off mode, power is removed from the instrument and no subsystems arepowered.

In standby mode, it is desirable to remove power from as many systems aspossible to reduce power consumption. Reduced power consumption leads toreduced thermal emissions from the electronics and reduces therequirement for active cooling systems such as fans. The elimination ofthe requirement for active cooling systems during standby mode has thedesirable effect of further decreasing the power consumption andreducing noise generation when the device is not in use by the user.

A problem that arises when trying to remove power from as manysubsystems as possible occurs when one or more systems or integratedcircuits comprise integrated pull up resistors. FIG. 1, illustrates acommonly employed method of charging a data bus line (150) andillustrates the problems that occur when more than one subsystem (130,140) is attached to the same data bus line (150), each with theirrespective integrated pull up resistor (135, 145). When the system shownin FIG. 1 is operating in the run mode, voltage is applied at both thesecond power supply (120) and the first power supply (110). When thesystem is put into standby mode and only subsystem 2 (140) is requiredto maintain standby operations, it is desirable to remove power fromsubsystem 1 (130) while maintaining power to subsystem 2 (140). Aproblem now occurs because once the first power supply (110) is set tozero volts, the combination of a first resistor (135) and a secondresistor (145) become a voltage divider for the second power supply(120) and the data bus line (150) voltage drops to a less than desirablelevel as a result of the divided voltage between the second power supplylevel (120) and zero volts. It would therefore be desirable to removethe first resistor (135) and have the second resistor (145) apply therequired charge the bus line (150). However often subsystems aredesigned or fabricated by outside entities and come with integrated pullup resistors that cannot be easily removed. This is especially true withintegrated circuits where the pull up resistors are internal to theintegrated circuit and cannot be removed. It would be desirable to findan alternate method to be able to remove the voltage from a firstsubsystem (130) and maintaining voltage for a second subsystem (140),while avoiding the undesirable effects of divided voltage describedabove and without requiring the removal of the pull up resistor of thepowered down subsystem.

SUMMARY OF THE INVENTION

In accordance with an aspect of the present invention, an apparatushaving a first mode of operation and a second mode of operationcomprising a data bus, a first power supply operating in said firstmode, a second power supply operating in said first mode, a third powersupply operating in said first mode and said second mode; and atransistor with a base, collector and emitter wherein said first powersupply is electrically coupled to the base, the second power supplybeing electrically coupled to the collector, the signal line beingelectrically coupled to the emitter and the third power supply beingelectrically coupled to the signal line wherein said transistor isforward biased during said first mode and reverse biased during saidsecond mode.

BRIEF DESCRIPTION OF THE DRAWING

The above-mentioned and other features and advantages of this invention,and the manner of attaining them, will become more apparent and theinvention will be better understood by reference to the followingdescription of embodiments of the invention taken in conjunction withthe accompanying drawings, wherein:

FIG. 1 is a circuit diagram of a data bus line with pull up resistorsintegral to their respective subsystems according to the prior art.

FIG. 2 is a block diagram of a data bus line with pull up resistorsintegral to their respective subsystems circuitry according to a firstexemplary embodiment of the present invention.

FIG. 3 is a block diagram of a data bus line with pull up resistorsintegral to their respective subsystems circuitry according to a secondexemplary embodiment of the present invention.

FIG. 4 is a block diagram of a data bus line with pull up resistorsintegral to their respective subsystems circuitry according to a thirdexemplary embodiment of the present invention.

FIG. 5 is a block diagram of a data bus line with pull up resistorsintegral to their respective subsystems circuitry according to a fourthexemplary embodiment of the present invention.

FIG. 6 is a state diagram of an exemplary embodiment of the operation ofcircuitry according to the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The exemplifications set out herein illustrate preferred embodiments ofthe invention, and such exemplifications are not to be construed aslimiting the scope of the invention in any manner.

Referring to FIG. 1, a circuit diagram of a data bus line with pull upresistors integral to their respective subsystems according to the priorart 100 is shown. The system depicted in FIG. 1, comprises a first powersupply 110, operative in a first mode of operation, a second powersupply 120, operative in the first mode of operation and a second modeof operation, a first subsystem 130, comprising a first pull upresistors 135, a second subsystem 140 comprising a second pull upresistor 145, wherein the first subsystem 130 and the second subsystem140 are both connected to at least one data bus line 150. The data busline could be, for example, an I²C bus line as is commonly used inconsumer electronics systems such as television signal processingapparatuses.

Referring to FIG. 2, a block diagram of a data bus line with pull upresistors integral to their respective subsystems circuitry according toa first exemplary embodiment of the present invention is shown. Thesystem depicted in FIG. 2, comprises a first power supply 210, operativein a first mode of operation, a second power supply 220, operative in afirst and second mode of operation, a first subsystem 230, comprising afirst pull up resistors 235, a second subsystem 240 comprising a secondpull up resistor 245, wherein the first subsystem 230 and the secondsubsystem 240 are both connected to at least one data bus line 250 and afirst transistor 260 wherein the base and collector of said transistor260 are connected to the first power supply 210, and the emitter of thetransistor is connected to the first subsystem 230 including aconnection to the pull up resistor 235 internal to the first subsystem230.

In this exemplary embodiment shown in FIG. 2, when the system 200 isoperating in the first mode of operation, a run mode, power is suppliedby both the first power supply 210 and the second power supply 220. Whenpower is applied by the first power supply 210 to the base of the firsttransistor 260, the transistor 260 becomes conductive between thecollector and emitter, and power is supplied to the first subsystem. Thepower supplied by the exemplary embodiment is approximately 0.7 voltsless than the power supplied to the base of the transistor 260 andsubsequently resulting in a 0.7 volt drop between the collector andemitter. A resistor network can be added to the base supply line and/orthe collector of the transistor 260 to ensure the transistor issaturated resulting in only a 0.2 volt drop between the collector andthe emitter of the transistor 260. When the system 200 is placed in thesecond mode of operation, a standby mode where some of the subsystemsare powered down to reduce energy consumption and heat generation, poweris removed from the first power supply 210. Power is still supplied tosubsystem 2 240 by the second power supply 220. The data bus line ischarged through the second pull up resistor 245 internal to subsystem 2240. This pull up voltage on the data bus line 250 results in a reversebias of the first transistor 260 electrically disconnecting the data busline 250 from the first power supply 210.

Referring to FIG. 3, a block diagram of a data bus line with pull upresistors integral to their respective subsystems circuitry according toa second exemplary embodiment of the present invention is shown. Thesystem depicted in FIG. 3, comprises a first power supply 310, operativein a first mode of operation, a second power supply 320, operative in afirst and second mode of operation, a third power supply 370 operativein a first mode of operation, a first subsystem 330, comprising a firstpull up resistors 335, a second subsystem 340 comprising a second pullup resistor 345, wherein the first subsystem 330 and the secondsubsystem 340 are both connected to at least one data bus line 350 and afirst transistor 360 wherein the collector of said transistor 360 isconnected to the first power supply 310, the base of said transistor 360is connected to the third power supply and the emitter of the transistoris connected to the first subsystem 330 including a connection to thepull up resistor 335 internal to the first subsystem 330.

In this exemplary embodiment shown in FIG. 3, when the system 300 isoperating in the first mode of operation, a run mode, power is suppliedby the first power supply 310 and the second power supply 320 and thethird power supply 370. When power is applied by the third power supply370 to the base of the first transistor 360, the transistor 360 becomesconductive between the collector and emitter, and power is supplied tothe first subsystem. The power supplied by the third power supply 370can be chosen to have a value high enough to ensure the transistor issaturated resulting in only a 0.2 volt drop between the collector andthe emitter of the transistor 360. The voltage level supplied to thebase of the transistor 360 can also be adjusted by supplying a resistivenetwork between the third power supply 370 and the base of thetransistor 360. When the system 300 is placed in the second mode ofoperation, a standby mode where some of the subsystems are powered downto reduce energy consumption and heat generation, power is removed fromthe first power supply 310 and the third power supply 370. Power isstill supplied to subsystem 2 340 by the second power supply 320. Thedata bus line is charged through the second pull up resistor 345internal to subsystem 2 340. This pull up voltage on the data bus line350 results in a reverse bias of the first transistor 360 electricallydisconnecting the data bus line 350 from the first power supply 310.

Referring to FIG. 4, a block diagram of a data bus line with pull upresistors integral to their respective subsystems circuitry according toa third exemplary embodiment of the present invention is shown. Thesystem depicted in FIG. 4, comprises a first power supply 410, operativein a first mode of operation, a second power supply 420, operative in afirst and second mode of operation, a source of a control signal 470, afirst subsystem 430, comprising a first pull up resistors 435, a secondsubsystem 440 comprising a second pull up resistor 445, wherein thefirst subsystem 430 and the second subsystem 440 are both connected toat least one data bus line 450 and a first transistor 460 wherein thecollector of said transistor 460 is connected to the first power supply410, the base of said transistor 460 is connected to the source of acontrol signal 470 and the emitter of the transistor is connected to thefirst subsystem 430 including a connection to the pull up resistor 435internal to the first subsystem 430.

In this exemplary embodiment shown in FIG. 4, when the system 400 isoperating in the first mode of operation, a run mode, a control signalis applied to the base of the first transistor 460 by a source of acontrol signal 470, such as a microprocessor or a discrete analogcircuit, power is supplied by the first power supply 410 and the secondpower supply 420. When the control signal is applied to the base of thefirst transistor 460, the transistor 460 becomes conductive between thecollector and emitter, and power from the first power supply 410 issupplied to the first subsystem. The level of the control signal shouldbe chosen to have a voltage level high enough to ensure the transistoris saturated resulting in only a 0.2 volt drop between the collector andthe emitter of the transistor 460 to ensure that the voltage levelsupplied to the first subsystem 430 is as close to the voltage level ofthe first power supply 410 as possible. When the system 400 is placed inthe second mode of operation, a standby mode where some of thesubsystems are powered down to reduce energy consumption and heatgeneration, the control signal is removed from the base of thetransistor 460. The first power supply 410 voltage may be reduced,turned off, or left at its full voltage level depending on theapplication. Power is still supplied to subsystem 2 440 by the secondpower supply 420. The data bus line is charged through the second pullup resistor 445 internal to subsystem 2 440. This pull up voltage on thedata bus line 450 results in a reverse bias of the first transistor 460electrically disconnecting the data bus line 450 from the first powersupply 410.

Referring to FIG. 5, a block diagram of a data bus line with pull upresistors integral to their respective subsystems circuitry according toa fourth exemplary embodiment of the present invention is shown. Thesystem depicted in FIG. 5, comprises a first power supply 510, operativein a first mode of operation and second mode of operation, a source of acontrol signal 570, a first subsystem 530, comprising a first pull upresistors 535, a second subsystem 540 comprising a second pull upresistor 545, wherein the first subsystem 530 and the second subsystem540 are both connected to at least one data bus line 550 and a firsttransistor 560 wherein the collector of said transistor 560 is connectedto the first power supply 510, the base of said transistor 560 isconnected to the source of a control signal 570 and the emitter of thetransistor is connected to the first subsystem 530 including aconnection to the pull up resistor 535 internal to the first subsystem530.

In this exemplary embodiment shown in FIG. 5, when the system 500 isoperating in the first mode of operation, a run mode, a control signalis applied to the base of the first transistor 560 by a source of acontrol signal 570, such as a microprocessor or a discrete analogcircuit, power is supplied by the first power supply 510. The source ofthe control signal 570 can also be a second power supply operative inonly the first mode of operation, having a voltage high enough toforward bias the transistor 560 only in the first mode of operation anda voltage low enough in the second mode of operation to reverse bias thetransistor 560 in the second mode of operation. When the signal isapplied to the base of the first transistor 560, the transistor 560becomes conductive between the collector and emitter, and power from thefirst power supply 510 is supplied to the first subsystem. The level ofthe control signal should be chosen to have a voltage level high enoughto ensure the transistor is saturated resulting in only a 0.2 volt dropbetween the collector and the emitter of the transistor 560 to ensurethat the voltage level supplied to the first subsystem 530 is as closeto the voltage level of the first power supply 510 as possible. When thesystem 500 is placed in the second mode of operation, a standby modewhere some of the subsystems are powered down to reduce energyconsumption and heat generation, the control signal is removed from thebase of the transistor 560. Power is supplied to subsystem 2 540 by thefirst power supply 510. The data bus line is charged through the secondpull up resistor 545 internal to subsystem 2 540. This pull up voltageon the data bus line 550 results in a reverse bias of the firsttransistor 560 electrically disconnecting the data bus line 550 from thefirst power supply 510.

Referring to FIG. 6 a state diagram 600 of an exemplary embodiment ofthe operation of circuitry according to the present invention is shown.When the system is in a first mode of operation 630, the run mode, allsystems that are required for the normal operation of the system arepowered and operating. In the run mode, active cooling devices, such asfans, are acceptable and can be used because the user expects and cantolerate some operating noise during this mode mode. However, when thesystem is in the second mode of operation 610, the standby mode, thesystem is perceived by the user to be off and the noise generated byactive devices is less acceptable. When a user decides to transition thesystem between the first mode of operation 630 and the second mode ofoperation 610, a first transition 620 is made wherein the power isremoved from the base of the transistor as shown in the previous figuresand voltage is removed from systems not required for operation in thestandby mode. When a user decides to transition the system between thesecond mode of operation 610 and the first mode of operation 630, asecond transition 640 is made wherein the voltage is applied to the baseof the transistor as shown in the previous figures and power is appliedto systems required for operation in the run mode.

1. An apparatus having a first mode of operation and a second mode of operation comprising: a data bus; a first power supply operating in said first mode, but not in said second mode; a second power supply operating in said first mode and said second mode; a third power supply operating in said first mode, but not in said second mode; and a transistor with a base, collector and emitter wherein said third power supply is electrically coupled to the base, said first power supply being electrically coupled to the collector, said data bus being electrically coupled to the emitter and said second power supply being electrically coupled to said data bus; wherein said transistor electrically isolates said data bus from said first power supply in said second mode of operation and electrically connects said data bus to said first power supply in said first mode of operation.
 2. The apparatus of claim 1 wherein said data bus is connected to the emitter via a resistor.
 3. The apparatus of claim 2 wherein the resistor is located within a subsystem.
 4. The apparatus of claim 3 wherein said subsystem is an integrated circuit.
 5. An apparatus having a first mode of operation and a second mode of operation comprising: a data bus; a first power supply operating in said first mode, but not in said second mode; a second power supply operating in said first mode and said second mode; a transistor, responsive to a first power supply voltage level, with a base, collector and emitter wherein said first power supply is electrically coupled to base and collector, said data bus line being electrically coupled to the emitter, and said second power supply being electrically coupled to said data bus; wherein said transistor electrically isolates said data bus from said first power supply in said second mode of operation and electrically connects said data bus to said first power supply in said first mode of operation.
 6. The apparatus of claim 5 wherein the data bus is connected to the transistor via a resistor.
 7. The apparatus of claim 6 wherein the resistor is located within subsystem.
 8. The apparatus of claim 7 wherein said subsystem is an integrated circuit.
 9. An apparatus having a first mode of operation and a second mode of operation comprising: a data bus; a power supply operating in said first mode and said second mode; a control signal active in said first mode; and a transistor, responsive to said control signal, with a base, collector and emitter wherein said power supply is electrically coupled to said collector and said data bus, said control signal is electrically coupled to said base, said data bus electrically coupled to the emitter; wherein said transistor electrically isolates said data bus from said power supply in said second mode of operation and electrically connects said data bus to said power supply in said first mode of operation.
 10. The apparatus of claim 9 wherein the data bus is connected to the transistor via a resistor
 11. The apparatus of claim 10 wherein the resistor is located within a subsystem.
 12. The apparatus of claim 11 wherein said subsystem is an integrated circuit.
 13. A television signal processing apparatus having a first mode of operation and a second mode of operation comprising: a data bus; a first subsystem operative in said first mode of operation; a second subsystem operative in said first mode of operation and said second mode of operation; a control signal active in said first mode; and a transistor, responsive to said control signal, wherein said first subsystem and said second subsystem are both connected to said data bus; wherein said data bus is connected to a first power supply via a first resistor integrated within said first subsystem and said data bus is connected to a second power supply via a second resistor integrated within said second subsystem; and wherein said first resistor is electrically isolated from said first power supply during said second mode of operation and electrically connected to said first power supply during said first mode of operation by said transistor.
 14. The television signal processing apparatus of claim 13 wherein said first subsystem is an integrated circuit.
 15. The television signal processing apparatus of claim 13 wherein said second subsystem is an integrated circuit. 